
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.state_pkg.all;

entity error_state_ctrl is
port (clk			: in	std_logic;
		reset			: in	std_logic;
		continu : out std_logic;
		rover_direction : out direction_type;
		
		dbm : out string (2 downto 1)
	);
end error_state_ctrl;

architecture Behavioral of error_state_ctrl is
		type		error_state_ctrl_state is ( 	active,
															inactive);
															
		signal state:			error_state_ctrl_state;
		
begin

		process (clk)
			begin
						if (rising_edge (clk)) then
								if ( reset = '1') then
										state <= inactive;
								else
										state <= active;
								end if;
						end if;
			end process;
			
			
		process (state)
			begin
						case state is
								
								when inactive =>
										rover_direction <= STOP;
										continu			 <= '0';
										dbm				 <= "IA";
										
								when active =>
										rover_direction <= STOP;
										continu			 <= '1';
										dbm				 <= "AC";
										
						end case;
			end process;

end architecture Behavioral;

